`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:37:10 07/30/2015
// Design Name:   HazardUnit
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/HazardTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: HazardUnit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module HazardTest;

	// Inputs
	reg memReadE3;
	reg [4:0] RtE3;
	reg [4:0] RsE2;
	reg [4:0] RtE2;

	// Outputs
	wire stallone;

	// Instantiate the Unit Under Test (UUT)
	HazardUnit uut (
		.memReadE3(memReadE3), 
		.RtE3(RtE3), 
		.RsE2(RsE2), 
		.RtE2(RtE2), 
		.stallone(stallone)
	);

	initial begin
		// Initialize Inputs
		memReadE3 = 0;
		RtE3 = 0;
		RsE2 = 0;
		RtE2 = 0;

		// Wait 100 ns for global reset to finish
		#100;
      //lw 2, addr
		//and 4,2,5
		memReadE3 = 1;
		RtE3 = 2;
		RsE2 = 2;
		RtE2 = 5;
		#100;
      //lw 2, addr
		//and 4,5,2
		memReadE3 = 1;
		RtE3 = 2;
		RtE2 = 2;
		RsE2 = 5;
		// Add stimulus here
		#100;
		memReadE3 = 0;

	end
      
endmodule

